During the 2017 Symposia on VLSI Technology and Circuits, imec  reported record breaking values below 10^-9 Ohm.cm² for PMOS source/drain contact resistivity. These results were obtained through shallow gallium implantation on p-SiliconGermanium (p-SiGe) source/drain contacts with subsequent pulsed nanosecond laser anneal.   In future N7/N5 nodes, the source/drain contact area of the transistors becomes so small that the contact resistance threatens to become the dominating parasitic factor, r...